1. Technical Field
The present invention relates to a semiconductor memory device having memory cells each connected with a word line and a bit line and being operable in a normal operation mode/a test operation mode which can be set.
2. Description of the Related Art
For the recent semiconductor memory devices, there is an increasing demand to speed up procedures of reading/writing data as the speed of CPU's processing increases. For this reason, not only speeding up the operation clock but also a reduction in a time period from the time at which a command is input to a time at which a subsequent command can be input, is required.
One example of such a predetermined time period which is required from the input of a command to the input of the subsequent command is a time period tRCD from the time at which an active command used in SDRAM (Synchronous DRAM) is input to a time at which a read command for reading data or a write command for writing data can be input.
In general, in a semiconductor memory device, a test (hereinafter referred to as “tRCD test”) is performed wherein a read or write command is input after the tRPCD time is elapsed from the input of an active command and it is determined whether or not the semiconductor memory device operates properly.
One example of a method of the tRCD test is disclosed in JP2003-346497A, for example. This patent literature describes in embodiment 1 that an active address is input at the time of input of precharge command PRE after the input of a mode set command, and describes in embodiment 2 that active command ACT and command PACT (a command for latching a low address alone) are input without it being necessary to input an address when active command ACT is input, thus allowing the time of LRCD to be checked.
However, in the case of embodiment 1 of the patent literature, each time a check of all combinations of addresses is made, a mode set command and a precharge command must be input, making the test time lengthy. In the case of embodiment 2 of the patent literature, in which an additional command is input, this command is generated by the combination of RAS, CAS, WE and CAS, and only the combination in which CS is fixed at a level other than a low level (a high level) is left. Therefore, when CS is fixed at a low level in order to concurrently check plural chips, such as when a wafer test is performed, it is impossible to implement the method according to embodiment 2 of the aforementioned patent literature.
The aforementioned tRCD test is performed as part of a wafer screening test. In recent years, in order to increase the number of chips that are concurrently tested in the wafer screening test, a test method (an address degeneracy method) has been proposed wherein in order to reduce the number of driver pins of a tester which are assigned to one chip, an address is latched at both falling and rising edges of a clock signal CLK, allowing different addresses to be entered from common driver pins.
FIG. 1 is a block diagram of a semiconductor memory device which is subjected to such a tRCD test. This semiconductor memory device comprises clock generator 1, address buffer 2, command decoder 9, row decoder 4, column decoder 5 and memory cell array 6.
Memory cell array 6 has a configuration identical to a conventional memory cell array and includes memory cells, word lines, bit lines, sense amplifiers and the like, and inputs/outputs data DQ. Memory cell array 6 also includes Y switches for outputting data on a predetermined bit line to the outside. Selection of a predetermined memory cell is performed by selecting a word line corresponding to a row address that is input from the outside and then selecting a bit line corresponding to a column address that is input from the outside, that is, by turning a corresponding Y switch on.
Clock generator 1 receives clock signals CLK, /CLK, clock enable signal CKE and test mode signal TMD and outputs signals PCLK, PCLKC, TPCLKB. Signal PCLK is a one-shot signal that is generated from a rising edge of clock signal CLK and is used as a pulse signal for latching a command that is input. Signal PCLKC is also a one-shot signal that is generated from a rising edge of clock signal CLK, but is used as a pulse signal for latching an address ADR that is input to address buffer 2 from the outside. Since address buffer 2 and command decoder 9 are distant from one another, signal PCLKC, which is separate from signal PCLK is supplied to address buffer 2. Signal TPCLKB is a one-shot signal that is generated from the falling edge of clock signal CLK, and is used as a pulse signal for latching an address that is input to address buffer 2. Test mode signal TMD is a signal that goes high when the tRCD test is performed. As shown in FIG. 2, clock generator 1 is comprised of inverters 401 to 403, delay circuits 404, 405, AND gate 406, NAND gate 407 and inverters 408, 409.
Address buffer 2 receives 12-bit address ADR, test mode signal TMD and signals PCLKC, TPCLKB, and outputs address signals CIA0 to CIA11. As shown in FIG. 3, address buffer 3 is comprised of inverter 40, buffers 41-0, 41-1, . . . , 41-11, D flip-flops 42-0, 42-2, . . . , 42-10, transfer gates 43-0, 43-1, . . . , 43-11, D flip-flops 44-0, 44-1, . . . , 44-11, buffers 45-0, 45-1, 45-11. During the normal operation, test mode signal TMD is at a low level, so that transfer gates 43-0, 43-2, . . . , and 43-10 are turned off and transfer gates 43-1, 43-3, . . . , and 43-11 are turned on. Accordingly, address signals PAD0, PAD1, . . . , PAD11 that are input from respective address terminals ADR0, ADR1, . . . , ADR11, are latched to respective D flip-flops 44-0, 44-1, . . . , 44-11 by signal PCLKC, and are output to row decoder 4 and column decoder 5 through respective buffers 45-0, 45-1, . . . , 45-11 as address signal CIA0, CIA1, . . . , CIA11. During the tRCK test, test mode signal TMD is at a high level, so that transfer gates 43-0, 43-2, . . . , and 43-10 are turned on and transfer gates 43-1, 43-3, . . . , and 43-11 are turned off. Accordingly, address signals PAD0, PAD2, . . . , PAD10 that are input from address terminals ADR0, ADR2, . . . , ADR10, are latched to respective D flip-flops 42-0, 42-2, . . . , 42-10 by signal TPCLKCB, pass through respective transfer gates 43-0, 43-2, . . . , 43-10 and are also latched to respective D flip-flops 44-1, 44-3, . . . , 44-11 by signal PCLKC. That is, during the tRCK test, addresses, which are the same as the address signals latched to respective D flip-flops 44-0, 44-2, . . . , 44-10, are input only from the even-numbered address terminals ADR, ADR2, . . . , ADR10 and are latched to D flip-flops 44-1, 44-3, . . . , 44-11 for output.
Command decoder 9 receives chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, bank address signals BA0, BA1, signal PCLK, address signals CIA0 to CIA11, and outputs test mode signal TMD, signals RRASB, MEXAL, CEXAC and CYE.
Here, the reason why the number of the bank address signals is two (BA0, BA1) is that the semiconductor memory device shown in FIG. 1 has a 4-bank configuration. Signal RRASB is a signal that is at a low level from the time when active command ACT is input to the time when precharge command PRE is input. Signal MEXAL is a signal that is used, when active command ACT is input, for latching an address that is input at that time, as a row-side selection signal. Signal CEXAC is a signal that is used, when a write/read command is input, for latching an address that is input at that time, as a column-side selection signal. Signal CYE is a signal that is used, when a write/read command is input, as a selection time for Y switch.
As shown in FIG. 4, command decoder 9 is comprised of test command determination circuit 31, active command determination circuit 32, write/read command determination circuit 33, precharge command determination circuit 34, bank-side selection circuit 35, row-side selection circuit 36 and column-side selection circuit 37.
Test command determination circuit 31 receives address signals CIA0 to CIA11 and signal PCLK and outputs test mode signal TMD. Active command determination circuit 32 receives chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, and outputs signal RACT that goes high during the interval of latch signal PCLK when conditions for outputting active command ACT are satisfied. As shown in FIG. 5, active command determination circuit 32 is comprised of D flip-flops 501 to 504, inverters 505, 506 and AND gate 507. Write/read command determination circuit 33 receives chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE and outputs signals CEXAC and CYE. Signal CEXAC is used, when a write/read command is input, for latching an address that is input at that time, as a column-side selection signal. Signal CYE is a pulse signal that is output when a write/read command is input, as in signal CEXAC. Signal CYE is output on a path separate from the path of signal CEXAC for ease of time adjustment. As shown in FIG. 6, write/read command determination circuit 33 is comprised of D flip-flops 301, 302, 303, inverters 304, 305, AND gate 306 and inverters 307 to 310. Precharge command determination circuit 34 receives low-level chip select signal /CS row address strobe signal /RAS, write enable signal /WE, high-level column address strobe signal /CAS, and outputs precharge command PRE. Bank-side selection circuit 35 receives bank address signals BA0, BA1, signal PCLK and test mode signal TMD, and outputs bank selection signals CIBA_A to CIBA_D, CIBA1_B and CIBA_T. Bank selection signals CIBA_A to CIBA_D are signals that are used for selecting respective banks A to B and that are determined according to a combination of a high level/a low level of bank address signals BA0 and BA1. Bank selection signals CIBA_B and CIBA_T are also signals for selecting a bank, but are determined according to a high/a low level of bank address signal BA1 alone. The reason why bank address signal BA0 is not used is that a latch circuit in row decoder 4 that is connected with command decoder 9, is shared among banks A and B for the reduction thereof. As shown in FIG. 7, bank-side selection circuit 36 is comprised of D flip-flops 101, 102, AND gates 103 to 106, inverters 107 to 109 and OR gates 110 to 115. Row-side control circuit 36 receives signal RACT, bank selection signals CIBA_A to CIBA_D, CIBA1_B, CIBA_T, precharge command PRE and outputs signals RRASB_A to RRASB_D, MEXAL_V and MEXAL_G. Signals RRASB_A to RRASB_D are signals that are at a low level from the time at which active command ACT is input to the time at which precharge command PRE is input. Signal MEXAL is a signal that is used, when active command ACT is input, for latching an address that is input at that time, as a row-side selection signal. As shown in FIG. 8, row-side control circuit 36 is comprised of AND gates 201 to 206, D flip-flops 207 to 210 and inverters 211 to 214. D flip-flops 207 to 210 receive respective output signals MEXAL_A to MEXAL_D from the clock terminals and are reset by precharge command PRE. Output signals RRASB_A to RRASB_D control the operations of decoders in row decoder 4. Signals MEXAL_V and MEXAL_G control the update operation of latch circuits (D flip-flops) in row decoder 4. Column-side control circuit 37 receives bank selection signals CIBA_A to CIBA_D, signals RRASB_A to RRASB_D and signal CYE, and outputs signals CYE_A to CYE_D. Signals CYE_A to CYE_D are signals that are used, when the write/read command is input, as a selection time for the Y switches of respective banks A to D. As shown in FIG. 9, column-side control circuit 37 is comprised of inverters 601 to 604, NOR gates 605 to 608 and NAND gates 609 to 612.
Row decoder 4 latches address signals CIAxx (where xx=0 to 11) output from address buffer 2 by means of signals MEXAL_V and MEXAL_G output from row-side control circuit 36 in command decoder 9, and decodes word lines WL_A to WL_D by means of decoders that are controlled by signals RRASB_A to RRASB_D output from row-side control circuit 36. As shown in FIG. 10, row decoder 4 is comprised of flip-flops 701, 702, inverters 703 to 706 and decoders 707 to 710. The flip-flop 701 supplies a signal RXT0_xxV in common to the decoder 707,708. The flip-flop 702 supplies a signal RXT0_xxG in common to the decoder 709,710.
Column decoder 5 latches address signals CIAxx (where xx=00 to 11) output from address buffer 2 by means of signal CEXAC output from write/read command determination circuit 33 in command decoder 9. Column decoder 5 then decodes address signals CIAxx by means of signals CYE_A to CYE_D that are output from column-side control circuit 37 and outputs signals to select Y switches YSW_A to YSW_D. As shown in FIG. 11, column decoder 5 is comprised of D flip-flop 801, inverters 802 to 805 and decoders 806 to 809.
FIG. 12 is a timing diagram of the semiconductor memory device shown in FIG. 1 to illustrate the normal operation (addresses are not degenerated) thereof. When chip select signal /CS and row address strobe signal /RAS go low, column strobe signal /CAS and write enable signal /WE go high and therefore active command ACT is activated at time T1, then row address Row is input to address buffer 2 and is latched to D flip-flops 44-0, 44-1, . . . , 44-11 (FIG. 3) by means of signal PCLKC as addresses CIA0 to CIA11. When read command Read or write command Write is input at time T2 which is a time at which clock signal CLK next rises then column address Column is input to address buffer 2 and is latched to D flip-flops 44-0, 44-1, . . . , 44-11 (FIG. 3) by means of signal PCLKC as address CIA0 to CIA11.
FIG. 13 is a timing diagram of the semiconductor memory device shown in FIG. 1 to illustrate the operation thereof when addresses are degenerated to one-half. In FIG. 13, several contents are denoted by the same reference characters as FIG. 12 to omit the further descriptions thereof. In this case, address mode signal TMD is rendered a high level. Even-numbered row address Row1 of address ADR: PAD0, PAD2, PAD4, . . . are latched by means of latch pulse PCLKC that is generated in synchronization with the rising of clock signal CLK, and are output as addresses CIA0, CIA2, CIA4, . . . . Next, odd-numbered row address Row2 of address ADR: PAD1, PAD3, . . . are input from even-numbered terminals of address buffer 2, and are latched to D flip-flops 42-0, 42-2, . . . by means of latch pulse TPCLKB that is generated in synchronization with the falling of clock signal CLK. Addresses PAD1, PAD3, . . . then pass through respective transfer gates 43-0, 43-2, . . . and are latched to respective D flip-flops 44-1, 44-3, . . . by means of latch pulse PCLKC. Similarly, even-numbered column address Column1 and odd-numbered column address Column2 are input to address buffer 2 by time T2 at which read command Read or write command Write is input, and are output as address signals CIA0 to CIA11.
FIG. 14 is a timing diagram of the semiconductor memory device shown in FIG. 1 to illustrate the operation of the command decoder when tRCD check is performed. In FIG. 14, several contents are denoted by the same reference characters as FIG. 12 to omit the further descriptions thereof.
First, a description is made of the operation when active command ACT is input at time T1. When clock signal CLK goes high, a high level one-shot signal is generated by clock generator 1 as signal PCLK. At this time, active command ACT is activated because chip select signal /CS and row address strobe signal /RAS are at a low level and column address strobe signal /CAS and write enable signal /WE are at high level. When active command ACT is activated, active command determination circuit 32 renders its output signal RACT high, the width of which is identical to the width of signal PCLK. When test mode signal TMD is at a high level, signals CIBA_A to CIBA_D, CIBA1_B and CIBA_T that are output from bank-side selection circuit 35 are all at a high level. As a result of signal RACT being rendered high, internal signals MEXAL_A to MEXAL_D and output signals MEXAL_V and MEXAL_G of row-side control circuit 36 are also rendered high, and hence output signals RRASB_A to RRASB_D of inverters 211 to 214 (FIG. 8) are rendered low. Addresses CIA0 to CIA11 are output with the input of address signals when the active command is activated. Signals RXT0_xxV and RXT0_xxG (where xx=00 to 11) are output with the input of signals MEXAL_V and MEXAL_G. Decoders 707 to 710 (FIG. 10) are operated through the input of low-level signals RRASB_A to RRASB_D, with the result that word lines WL_A,B,C,D to which an address of memory cell array 6 is input is selected.
Next, a description is made of an operation when a write or read command is entered at time T2. As with the operation at time T1, at time T2 as well, a high level one-shot signal is generated as signal PCLK. At this time, since the read or write command is input (chip select signal /CS is at a low level, row address strobe signal /RAS is at a high level and column address strobe signal /CAS is at low level), write/read command determination circuit 33 renders its output signals CEXAC and CYE high, the widths of which are identical to the width of signal PCLK. As explained hereinabove, since signals RRASB_A to RRASB_D are at a low level and signals CIBA_A to CIBA_D are at a high level, column-side control circuit 37 renders its output signals CYE_A to CYE_D low, the widths of which are identical to the width of signal CYE. As with the operation when active command ACT is activated, addresses CIA0 to CIA11 are output that correspond to the address signals that are input when the active command is activated, and signal CYxx is output through the input of signal CEXAC. Decoders 806 to 809 (FIG. 11) are operated through the input of low-level signals CYE_A to CYE_D, with the result that any one of Y switches YSW_A to YSW_D is selected. Thereafter, the time period tRCD between time T1 at which the active command is input and T2 at which the read or write command is input, i.e., between the time at which a word line is selected and the time at which a Y switch is selected, is measured and its shortness is evaluated as the performance of tRCD.
Thus, addresses of a semiconductor memory device, when they are not degenerated, are entered from corresponding address pins in synchronization with a falling edge or rising edge of the clock signal CLK. On the other hand, when addresses of a semiconductor memory device are degenerated, for example, address pins are reduced to one-half, different addresses are entered from address pins (even-numbered pins in the above example) from which addresses can be entered at the time of address degeneracy, in synchronization with both falling and rising edges of clock signal CLK. When address degeneracy is not performed (including a normal operation), tRCD does not depend on the amount of time that is used to capture addresses, as shown in FIG. 12. The reason for this is that because addresses are entered in synchronization with one of the falling and rising edges of clock signal CLK, it is possible to take an ample amount of time to capture row addresses and to capture column addresses. Meanwhile, when address degeneracy is performed, there arises a case in which the performance of tRCD cannot be precisely measured due to the influence of the amount of time that is used to capture column address Column1. That is, tRCD that should not depend on the amount of time that is used to capture addresses at the normal operation, depends on the amount of time that is used to capture addresses at the address degeneracy test. Thus, accurate evaluation of tRCD at the address degeneracy test is made impossible.